1. Field of the Invention
The invention relates to a communication control apparatus which is used mainly in an Asynchronous Transfer Mode: hereinafter, referred to as ATM) communication system and, more particularly, to a communication control apparatus which is suitable for handling an ATM cell of a fixed length belonging to a plurality of VP (Virtual Paths) and VC (Virtual Channels) (hereinafter, both of them are integrated and called VC (Virtual Connection) and which controls a memory for assembling a variable-length information frame that is equal to or larger than one-cell payload length and relates to each VC that is, virtual connection.
2. Related Background Art
In a communication network which handles a frame (conveyance unit) of various information by an ATM cell of a fixed length, one end node of an ATM layer decomposes the frame into a plurality of ATM cells and transmits them to the other end node. The other end node assembles the original frame from the plurality of received ATM cells, thereby transmitting and receiving the information. An end node on the reception side in a communicating apparatus constructing such a pair of end nodes receives various ATM cells, once stores those ATM cells into a memory, assembles them again, and forms the frame.
Hitherto, as such a kind of apparatus, for example, there are a construction of FIG. 2 in JP-A-5-110583 and a construction of FIG. 3 in JP-A10-285173. According to those constructions, a whole area in a memory is previously divided into corresponding areas every connection, for example, when an ATM cell belonging to a connection A is received, cell data is written into the memory area for the connection A, and when an ATM cell belonging to a connection B is received, cell data is written into the memory area for the connection B. In this manner, the data of each connection is accumulated, thereby realizing the assembly of the frame (such a technique is referred to as a prior art 1).
There is another method whereby a whole area in the memory is not divided into areas every connection but received cells are sequentially written into the memory in order, and annexed information of the cell data (that is, information showing to which connection the cell data belongs, or the like) is separately managed (such a technique is referred to as a prior art 2).
However, in the case where the frame assembly memory is controlled by the above prior arts, there are the following problems.                With respect to the prior art 1, when the cells regarding the same logical communication path, that is, the same connection are concentratedly received in a certain short time, in spite of the fact that an area as a whole memory is almost empty, only the area for such a connection is filled with the data and an overflow occurs. There is a problem from a viewpoint of the effective use of the memory.        With respect to the prior art 1, since it is not practical to also allow the memory areas to correspond to each of 228 (VPI (Virtual Path Identification)+VCI (Virtual Channel Identification)=28 bits) connections to which the ATM cells can inherently correspond, there is a problem such that it is necessary to apply some restriction with respect to connection numbers which can be handled on the system (a range of the connection numbers which can be used is limited, the connection number is converted into a local ID which is effective only in an apparatus, or the like).        With respect to the prior art 2, although the memory can be also effectively used at the time of the concentration on the same connection, since the frame assembly information needs to be separately managed, there is a problem such that hardware becomes complicated.        